`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/17 11:17:16
// Design Name: 
// Module Name: sram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module sram #(parameter addr_width = 7,parameter data_width = 128)(
    input CLK,
    input CS,
    input WE,
    input [addr_width-1:0] Addr,
    input [data_width-1:0] dataIn,
    output reg [data_width-1:0] dataOut
);
reg [data_width:0] SRAMs [(2**addr_width)-1:0];
/*
initial begin
    $readmemb("init_rams/DMA_AREAS.txt",SRAMs);
end
*/
always @ (posedge CLK)
begin
    if (CS == 1'b1) begin
        if (WE == 1'b1) begin SRAMs [Addr] <= dataIn; end
        dataOut <= SRAMs [Addr]; 
    end
end
endmodule

/*
module pingpong_sram#(parameter addr_width = 7,parameter data_width = 128)(
    input CLK,
    input rst,
    input rd_en,
    input wr_en,
    input rd_switch_req, //from RS reg
    input wr_switch_req, //from RS reg
    input [addr_width-1:0] rd_addr,
    input [addr_width-1:0] wr_addr,
    input [data_width-1:0] wr_data,
    output switch_done,     //to set0 pin of RS reg
    output [data_width-1:0] rd_data
);

wire wr_bank_en,wr_bank_din,wr_bank;
assign wr_bank_din=~wr_bank;
assign wr_bank_en=rd_switch_req&wr_switch_req;
assign switch_done=wr_bank_en;
regw #(.WIDTH(1)) WR_BANK(CLK,rst,wr_bank_en,wr_bank_din,wr_bank);

wire cs0,we0,cs1,we1;
assign cs0=((wr_bank==1'b0)&(wr_en==1'b1))|((wr_bank==1'b1)&(rd_en==1'b1));
assign cs1=((wr_bank==1'b1)&(wr_en==1'b1))|((wr_bank==1'b0)&(rd_en==1'b1));
assign we0=(wr_bank==1'b0)&(wr_en==1'b1);
assign we1=(wr_bank==1'b1)&(wr_en==1'b1);
wire [addr_width-1:0] addr0,addr1;
assign addr0=(wr_bank==0)?wr_addr:rd_addr;
assign addr1=(wr_bank==1)?wr_addr:rd_addr;
wire [data_width-1:0] dout0,dout1;

sram #(.addr_width(addr_width),.data_width(data_width)) BANK0(
    CLK,cs0,we0,addr0,wr_data,dout0);
sram #(.addr_width(addr_width),.data_width(data_width)) BANK1(
        CLK,cs1,we1,addr1,wr_data,dout1);
assign rd_data=(wr_bank==0)?dout1:dout0;
endmodule
*/